library verilog;
use verilog.vl_types.all;
entity DDS_AD9767 is
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        key             : in     vl_logic;
        data_A          : out    vl_logic_vector(13 downto 0);
        clk_A           : out    vl_logic;
        WRTA            : out    vl_logic;
        data_B          : out    vl_logic_vector(13 downto 0);
        clk_B           : out    vl_logic;
        WRTB            : out    vl_logic
    );
end DDS_AD9767;
